In its basic form, a field-effect transistor (FET) includes a source region, a drain region and a channel between the source and drain regions. A gate regulates electron flow through the channel between the source and drain regions.
FETs are used as the basic building blocks for many different types of complementary metal-oxide semiconductor (CMOS) circuitry. For example, logic gate inverters, a common component of many integrated circuit designs, can be formed using one or more complementary pairs of n-channel field-effect transistor (NFET) and p-channel field-effect transistor (PFET) devices. Typical NFET/PFET inverters are configured with the source region of the NFET being connected to the drain region of the PFET, and the gates of the devices being connected to one another.
This standard inverter layout, has a footprint the size of two FETs. Because of the prevalence of inverters in most circuit designs, reducing the layout footprint of the inverter could result in a significant reduction of layout area required to implement most circuit designs.
Therefore, scalable FET inverters and techniques for the fabrication thereof would be desirable.